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december 2014 docid018576 rev 4 1 / 95 this is information on a product in full production. www.st.com stm8s003k3 stm8s003f3 value line, 16 mhz stm8s 8 - bit mcu, 8 kbytes flash, 128 bytes data eeprom, 10 - bit adc, 3 timers, uart, spi, i2c datasheet - production data features core ? 16 mhz advanced stm8 core with harvard architecture and 3-stage pipeline ? extended instruction set memories ? program memory: 8 kbytes flash; data retention 20 years at 55 c after 100 cycles ? ram: 1 kbytes ? data memory: 128 bytes of true data eeprom; endurance up to 100 000 write/erase cycles clock, reset and supply management ? 2.95 to 5.5 v operating voltage ? flexible clock control, 4 master clock sources: ? low power crystal resonator oscillator ? external clock input ? internal, user-trimmable 16 mhz rc ? in ternal low power 128 khz rc ? clock security system with clock monitor ? power management: ? low power modes (wait, active-halt, halt) ? switch-off peripheral clocks individually ? permanently active, low consumption power- on and power-down reset interrupt management ? nested interrupt controller with 32 interrupts ? up to 27 external interrupts on 6 vectors timers ? advanced control timer: 16-bit, 4 capcom channels, 3 complementary outputs, dead- time insertion and flexible synchronization ? 16 -bit general purpose timer, with 3 capcom channels (ic, oc or pwm) ? 8-bit basic timer with 8-bit prescaler ? auto wake-up timer ? window watchdog and independent watchdog timers communications interfaces ? uart with clock output for synchronous operation, smartcard, irda, lin master mode ? spi interface up to 8 mbit/s ? i 2 c interface up to 400 kbit/s analog to digital converter (adc) ? 10 -bit, 1 lsb adc with up to 5 multiplexed channels, scan mode and analog watchdog i/os ? up to 28 i/os on a 32-pin package including 21 high sink outputs ? highly robust i/o design, immune against current injection development support ? embedded single wire interface module (swim) for fast on-chip programming and non intrusive debugging lqfp32 7 x 7 mm tssop20 4.4 x 6.4 mm ufqfpn20 3 x 3 mm
contents stm8s003k3 stm8s003f3 2 / 95 docid018576 rev 4 contents 1 introduction ................................ ................................ ..................... 8 2 description ................................ ................................ ....................... 9 3 block dia gram ................................ ................................ ................ 10 4 product overview ................................ ................................ .......... 11 4.1 central processing unit stm8 ................................ ......................... 11 4.2 single wire interface module (swim) and debug module (dm) ...... 12 4.3 interrupt controller ................................ ................................ ........... 12 4.4 flash program memory and data eeprom ................................ .... 12 4.5 clock controller ................................ ................................ ............... 14 4.6 power management ................................ ................................ ........ 15 4.7 watchdog timers ................................ ................................ ............. 15 4.8 auto wakeup counter ................................ ................................ ...... 16 4.9 beeper ................................ ................................ ............................ 16 4.10 tim1 - 16 - bit advanced control timer ................................ ............... 16 4.11 tim2 - 16 - bit general purpose timer ................................ ................ 16 4.12 tim4 - 8 - bit basic timer ................................ ................................ ... 17 4.13 analog - to - digital converter (adc1) ................................ ................. 17 4.14 communication interfaces ................................ ............................... 17 4.14.1 uart1 ................................ ................................ .............................. 18 4.14.2 spi ................................ ................................ ................................ .... 18 4.14.3 i2c ................................ ................................ ................................ ..... 18 5 pinout and pin description ................................ ........................... 20 5.1 stm8s003k3 lqfp32 pinout and pin description .......................... 21 5.2 stm8s003f3 tssop20/ufqfpn20 pinout and pin description .... 24 5.2.1 stm8s003f3 tssop20 pinout and pin description ........................ 24 5.2.2 stm8s003f3 ufqfpn20 pinout ................................ ..................... 25 5.2.3 stm8s003f3 tssop20/ufqfpn20 pin description ...................... 26 5.3 alternate function remapping ................................ .......................... 28 6 memory and register map ................................ ............................. 29 6.1 memory map ................................ ................................ ................... 29 6.2 register map ................................ ................................ ................... 30 6.2.1 i/o port hardware register map ................................ ........................ 30 6.2.2 general har dware register map ................................ ........................ 31
stm8s003k3 stm8s003f3 contents docid018576 rev 4 3 / 95 6.2.3 cpu/swim/debug module/interrupt controller registers .................. 37 7 interrupt vector mapping ................................ .............................. 39 8 option bytes ................................ ................................ .................. 40 8.1 alternate function remapping bits ................................ .................... 43 9 electrical characteristics ................................ .............................. 45 9.1 parameter conditions ................................ ................................ ...... 45 9.1.1 minimum and maximum values ................................ ........................ 45 9.1.2 typical values ................................ ................................ ................... 45 9.1.3 typical curves ................................ ................................ ................... 45 9.1.4 loading capacitor ................................ ................................ ............. 45 9.1.5 pin input voltage ................................ ................................ ............... 45 9.2 absolute maximum ratings ................................ .............................. 46 9.3 operating conditions ................................ ................................ ....... 48 9.3.1 vcap external capacitor ................................ ................................ .. 49 9.3.2 supply current characteristics ................................ .......................... 49 9.3.3 external clock sources and timing characteristics ............................ 59 9.3.4 internal clock sources and timing characteristics ............................. 61 9.3.5 memory characteristics ................................ ................................ ..... 63 9.3.6 i/o port pin characteristics ................................ ................................ 64 9.3.7 reset pin characteristics ................................ ................................ .. 72 9.3.8 spi serial peripheral interface ................................ .......................... 74 9.3.9 i2c interface characteristics ................................ ............................. 77 9.3.10 10 - bit adc characteristics ................................ ................................ 78 9.3.11 emc characteristics ................................ ................................ .......... 81 10 package information ................................ ................................ ..... 84 10.1 32 - pin lqfp package mechan ical data ................................ .......... 84 10.2 20 - pin tssop package mechanical data ................................ ....... 86 10.3 20 - lead ufqfpn package mechanical data ................................ ... 87 11 thermal characteristics ................................ ................................ 89 11.1 reference document ................................ ................................ ....... 89 11.2 selecting the product temperature range ................................ ........ 89 12 ordering information ................................ ................................ ..... 91 13 stm8 development tools ................................ .............................. 92 13.1 emulation and in - circuit debugging tools ................................ ......... 92 13.2 software tools ................................ ................................ ................. 92
contents stm8s003k3 stm8s003f3 4 / 95 docid018576 rev 4 13.2.1 stm8 toolset ................................ ................................ .................... 92 13.2.2 c and assembly toolchains ................................ .............................. 93 13.3 programming tools ................................ ................................ .......... 93 14 revision history ................................ ................................ ............ 94
stm8s003k3 stm8s003f3 list of tables docid018576 rev 4 5 / 95 list of tables table 1: stm8s003xx value line features ................................ ................................ ................................ .. 9 table 2: peripheral clock gating bit assignments in clk_pckenr1/2 registers ................................ .... 14 table 3: tim timer features ................................ ................................ ................................ ....................... 17 table 4: legend/abbreviat ions for pinout tables ................................ ................................ ....................... 20 table 5: lqfp32 pin description ................................ ................................ ................................ .............. 21 table 6: stm8s003f3 pin description ................................ ................................ ................................ ..... 26 table 7: i/o port hardware register map ................................ ................................ ................................ ... 30 table 8: gene ral hardware register map ................................ ................................ ................................ .. 31 table 9: cpu/swim/debug module/interrupt controller registers ................................ ............................ 37 table 10: interrupt mapping ................................ ................................ ................................ ...................... 39 ta ble 11: option bytes ................................ ................................ ................................ .............................. 40 table 12: option byte description ................................ ................................ ................................ ............. 41 table 13: stm8s003k3 alternate function remapping bits for 32 - pin devices ................................ ........ 43 table 14: stm8s003f3 alternate function remapping bits for 20 - pin devices ................................ ......... 44 table 15: voltage characteristics ................................ ................................ ................................ .............. 46 table 16: current characteristics ................................ ................................ ................................ .............. 47 table 17: thermal characteristics ................................ ................................ ................................ ............. 47 table 18: general o perating conditions ................................ ................................ ................................ .... 48 table 19: operating conditions at power - up/power - down ................................ ................................ ........ 49 table 20: total current consumption with code execution in run mode at vdd= 5 v .............................. 50 table 21: total current consumption with code execution in run mode at vdd= 3.3 v ........................... 51 table 22: total current consumption in wait mode at vdd= 5 v ................................ .............................. 52 table 23: total current consumption in wait mode at vdd= 3.3 v ................................ ........................... 52 table 24: total current consumption in active halt mode a t vdd= 5 v ................................ .................... 53 table 25: total current consumption in active halt mode at vdd= 3.3 v ................................ ................. 53 table 26: total current consumption in halt mode at vdd= 5 v ................................ .............................. 54 table 27: total current consumption in halt mode at vdd= 3.3 v ................................ ........................... 54 table 28: wakeup times ................................ ................................ ................................ ........................... 54 table 29: total current consumption and timing in forced reset state ................................ ...................... 56 table 30: peripheral current consumption ................................ ................................ ................................ 56 table 31: hse user external clock characteristics ................................ ................................ ................... 59 table 32: hse oscillator characteristics ................................ ................................ ................................ ... 60 table 33: hsi oscillator characteristics ................................ ................................ ................................ ..... 61 table 34: lsi oscillator characteristics ................................ ................................ ................................ ..... 62 table 35: ram and hardware registers ................................ ................................ ................................ .... 63 table 36: flash program memory and data eeprom ................................ ................................ ............. 63 table 3 7: i/o static characteristics ................................ ................................ ................................ ............ 64 table 38: output driving current (standard ports) ................................ ................................ ..................... 66 table 39: output driving current (true open drain ports) ................................ ................................ .......... 66 table 40: output driving current (high sink ports) ................................ ................................ .................... 66 table 41: nrst pin characteristics ................................ ................................ ................................ .......... 72 table 42: spi chara cteristics ................................ ................................ ................................ .................... 74 table 43: i2c characteristics ................................ ................................ ................................ .................... 77 table 44: adc characteristics ................................ ................................ ................................ .................. 78 table 45: adc accuracy with rain< 10 k , vdd= 5 v table 46: adc accuracy with rain< 10 k rain, vdd= 3.3 v
list of tables stm8s003k3 stm8s003f3 6 / 95 docid018576 rev 4 table 54: thermal characteristics ................................ ................................ ................................ ............. 89 table 55: document revision history ................................ ................................ ................................ ........ 94
stm8s003k3 stm8s003f3 list of figures docid018576 rev 4 7 / 95 list of figures figure 1: block diagram ................................ ................................ ................................ ............................ 10 figure 2: flash memory organization ................................ ................................ ................................ ....... 13 figure 3: stm8s003k3 lqfp32 pinout ................................ ................................ ................................ ... 21 figure 4: stm8s003f3 tssop20 pinout ................................ ................................ ................................ 24 figure 5 : stm8s003f3 ufqfpn20 - pin pinout ................................ ................................ ........................ 25 figure 6: memory map ................................ ................................ ................................ .............................. 29 figure 7: pin loading conditions ................................ ................................ ................................ ................ 45 figure 8: pin input voltage ................................ ................................ ................................ ........................ 45 figure 9: fcpumaxversus vdd ................................ ................................ ................................ ................ 48 figure 10: external capacitor cext ................................ ................................ ................................ ......... 49 figure 11: typ idd(run) vs. vdd hse user external clock, fcpu = 1 6 mhz ................................ ........ 57 figure 12: typ idd(run) vs. fcpu hse user external clock, vdd = 5 v ................................ ............... 57 figure 13: typ idd(run) vs. vdd hsi rc osc, fcpu = 16 mhz ................................ ............................ 58 figure 14: typ idd(wfi) vs. vdd hse user external clock, fcpu = 16 mhz ................................ ......... 58 figure 15: typ idd(wfi) vs. fcpu hse user external clock, vdd = 5 v ................................ ................ 58 figure 16: typ idd(wfi) vs. vdd hsi rc os c, fcpu = 16 mhz ................................ ............................. 59 figure 17: hse external clock source ................................ ................................ ................................ ...... 59 figure 18: hse oscillator circuit diagram ................................ ................................ ................................ .. 60 figure 19: typical hsi frequency variation vs vdd@ 4 temperatures ................................ .................... 62 figure 20: typical lsi frequency variation vs vdd@ 4 temperatures ................................ ..................... 62 figure 21: typical viland vihvs vdd@ 4 temperatures ................................ ................................ ........ 65 figure 22: typical pull - up resistance vs vdd@ 4 temperatures ................................ .............................. 65 figure 23: typical pull - up current vs vdd@ 4 temperatures ................................ ................................ ... 65 figure 24: typ. vol@ vdd= 5 v (standard ports) ................................ ................................ .................. 67 figure 25: typ. vol@ vdd= 3.3 v (standard ports) ................................ ................................ ............... 67 figure 26: typ. vol@ vdd= 5 v (true open drain ports) ................................ ................................ ........ 68 figure 27: typ. vol@ vdd= 3.3 v (true open drain ports) ................................ ................................ ..... 68 figure 28: typ. vol@ vdd= 5 v (high sink ports) ................................ ................................ .................. 69 figure 29: typ. vol@ vdd= 3.3 v (high sink ports) ................................ ................................ ............... 69 figure 30: typ. vdd - voh@ vdd= 5 v (standard ports) ................................ ................................ ........ 70 figure 31: typ. vdd - voh@ vdd= 3.3 v (standard ports) ................................ ................................ ..... 70 figure 32: typ. vdd - voh@ vdd= 5 v (high sink ports) ................................ ................................ ....... 71 f igure 33: typ. vdd - voh@ vdd= 3.3 v (high sink ports) ................................ ................................ .... 71 figure 34: typical nrst viland vihvs vdd @ 4 temperatures ................................ ............................. 72 figure 35: typical nrst pull - up resistance vs vdd@ 4 temperatures ................................ ................... 73 figure 36: typical nrst pull - up current vs vdd@ 4 temperatures ................................ ........................ 73 figure 37: recommended reset pin protection ................................ ................................ ........................ 74 figure 38: spi timing diagram - slave mode and cpha = 0 ................................ ................................ .... 75 figure 39: spi timing diagram - slave mode and cpha = 1 ................................ ................................ .... 75 figure 40: spi timing diagram - master mode(1) ................................ ................................ ..................... 76 figure 41: typical application with i2c bus and timing diagram ................................ .............................. 78 figure 42: adc accuracy characteristics ................................ ................................ ................................ .. 80 figure 43: typical application with adc ................................ ................................ ................................ ... 81 figure 44: 32 - pin low profile quad flat package (7 mm x 7 mm) ................................ .............................. 84 figure 45: 20 - pin, 4.40 mm body, 0.65 mm pitch ................................ ................................ ..................... 86 figure 46: 20 - lead, ultra thin, fine pitch quad flat no - lead package outline (3 x 3) ................................ ... 87 figure 47: stm8s003x value line ordering informat ion scheme ................................ .............................. 91
introduction stm8s003k3 stm8s003f3 8 / 95 docid018576 rev 4 1 introduction this datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information. x for complete information on the st m8s microcontroller memory, registers and peripherals, please refer to the stm8s microcontroller family reference manual (rm0016). x for information on programming, erasing and protection of the internal flash memory please refer to the stm8s flash programm ing manual (pm0051). x for information on the debug and swim (single wire interface module) refer to the stm8 swim communication protocol and debug module user manual (um0470). x for information on the stm8 core, please refer to the stm8 cpu programming manu al (pm0044).
stm8s003k3 stm8s003f3 description docid018576 rev 4 9 / 95 2 description the stm8s003x value line 8 - bit microcontrollers feature 8 kbytes flash program memory, plus integrated true data eeprom. the stm8s microcontroller famil y reference manual (rm0016) refers to devices in this family as low - density. they provide the following benefits: performance, robustness, and reduced system cost. device performance and robustness are ensured by integrated true data eeprom supporting up t o 100000 write/erase cycles, advanced core and peripherals made in a state - of - the art technology, a 16 mhz clock frequency, robust i/os, independent watchdogs with separate clock source, and a clock security system. the system cost is reduced thanks to hig h system integration level with internal clock oscillators, watchdog and brown - out reset. full documentation is offered as well as a wide choice of development tools. table 1: stm8s003xx value line features device stm8s003k3 stm8s003f3 pin count 32 20 maximum number of gpios (i/os) 28 16 ext. interrupt pins 27 16 timer capcom channels 7 7 timer complementary outputs 3 2 a/d converter channels 4 5 high sink i/os 21 12 low density flash program memory (bytes) 8k 8k ram (bytes) 1k 1k true data eeprom (bytes) (1) 128 128 peripheral set multipurpose timer (tim1), spi, i 2 c, uart window wdg,independent wdg, adc, pwm timer (tim2), 8 - bit timer (tim4) notes: (1) without read - while - write capability.
block diagram stm8s003k3 stm8s003f3 10 / 95 docid018576 rev 4 3 block diagram figure 1 : block diagram x t a l 1-16 mhz rc int. 16 mhz rc int. 128 khz stm8 core debug/swim spi ua r t1 16-bit general purpose a wu timer reset block reset por bor clock controller detector clock to peripherals and core 8 mbit/s lin master address and data bus window wdg 8-kbyte 1-kbyte adc1 4 capcom reset 400 kbit/s single wire debug interf. spi emul. channels +3 program flash 16-bit advanced control timer (tim1) 8-bit basic timer ram up to beeper 1/2/4 khz beep independent wdg (tim4) 3 capcom channels up to complementary outputs timer (tim2) up to 5 channels i 2 c 128-byte data eeprom
stm8s003k3 stm8s003f3 product overview docid018576 rev 4 11 / 95 4 product overview the following section int ends to give an overview of the basic features of the device functional modules and peripherals. for more detailed information please refer to the corresponding family reference manual (rm0016). 4.1 central processing unit stm8 the 8 - bit stm8 core is designed for code efficiency and performance. it contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions. architecture and registers x harvard architecture x 3 - stage pipeline x 32 - bi t wide program memory bus - single cycle fetching for most instructions x x and y 16 - bit index registers - enabling indexed addressing modes with or without offset and read - modify - write type data manipulations x 8 - bit accumulator x 24 - bit program counter - 16 - mbyte linear memory space x 16 - bit stack pointer - access to a 64 k - level stack x 8 - bit condition code register - 7 condition flags for the result of the last instruction addressing x 20 addressing modes x indexed indirect addressing mode for look - up tables l ocated anywhere in the address space x stack pointer relative addressing mode for local variables and parameter passing instruction set x 80 instructions with 2 - byte average instruction size x standard data movement and logic/arithmetic functions x 8 - bit by 8 - bit multiplication x 16 - bit by 8 - bit and 16 - bit by 16 - bit division x bit manipulation x data transfer between stack and accumulator (push/pop) with direct stack access x data transfer using the x and y registers or direct memory - to - memory transfers
product overview stm8s003k3 stm8s003f3 12 / 95 docid018576 rev 4 4.2 single wir e interface module (swim) and debug module (dm) the single wire interface module and debug module permits non - intrusive, real - time in - circuit debugg ing and fast memory programming. swim single wire interface module for direct access to the debug module and memory programming. the interface can be activated in all device operation modes. the maximum data transmission speed is 145 bytes/ms. debug modu le the non - intrusive debugging module features a performance close to a full - featured emulator. beside memory and peripherals, also cpu operation can be monitored in real - time by means of shadow registers. x r/w to ram and peripheral registers in real - time x r/w access to all resources by stalling the cpu x breakpoints on all program - memory instructions (software breakpoints) x two advanced breakpoints, 23 predefined configurations 4.3 interrupt controller x nested interrupts with three software priority levels x 32 interrupt vectors with hardware priority x up to 27 external interrupts on 6 vectors including tli x trap and reset interrupts 4.4 flash program memory and data eeprom x 8 kbytes of flash program single voltage flash memory x 128 bytes of true data eeprom x user option byte area write protection (wp) write protection of flash progra m memory and data eeprom is provided to avoid unintentional overwriting of memory that could result from a user software malfunction. there are two levels of write protection. the first level is known as mass (memory access security system). mass is alway s enabled and protects the main flash program memory, the data eeprom, and the option bytes. to perform in - application programming (iap), this write protection can be removed by writing a mass key sequence in a control register. this allows the applicatio n to modify the content of the main program memory and data eeprom, or to reprogram the device option bytes. a second level of write protection, can be enabled to further protect a specific area of memory known as ubc (user boot code). refer to the figure below. the size of the ubc is programmable through the ubc option byte, in increments of 1 page (64 - byte block) by programming the ubc option byte in icp mode. this divides the program memory into two areas: x main program memory: 8 kbytes minus ubc x user - specific boot code (ubc): configurable up to 8 kbytes
stm8s003k3 stm8s003f3 product overview docid018576 rev 4 1 3 / 95 the ubc area remains write - protected during in - application programming. this means that the mass keys do not unlock the ubc area. it protects the memory used to store the boot program, specific co de libraries, reset and interrupt vectors, the reset routine and usually the iap and communication routines. figure 2 : flash memory organization read - out protection (rop) the read - out protection blocks reading and writing from/to the flash program memory and the data eeprom in icp mode (and debug mode). once the read - out protection is activated, any attempt to toggle its status triggers a global erase of the program memory. even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.
product overview stm8s003k3 stm8s003f3 14 / 95 docid018576 rev 4 4.5 clock controller the clock controller distributes the system clock (f master ) coming from different oscillators to the core and the peripherals. it also manages clock gating for low power modes and ensures clock robustness. features x clock prescaler: to get the best comprom ise between speed and current consumption the clock frequency to the cpu and peripherals can be adjusted by a programmable prescaler. x safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. the cloc k signal is not switched until the new clock source is ready. the design guarantees glitch - free switching. x clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. x master clock sou rces: four different clock sources can be used to drive the master clock: 1 - 16 mhz high - speed external crystal (hse) up to 16 mhz high - speed user - external clock (hse user - ext) 16 mhz high - speed internal rc oscillator (hsi) 128 khz low - speed internal rc (lsi ) x startup clock: after reset, the microcontroller restarts by default with an internal 2 mhz clock (hsi/8). the prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. x clock security system (css): this feature can be enabled by software. if an hse clock failure occurs, the internal rc (16 mhz/8) is automatically selected by the css and an interrupt can optionally be generated. x configurable main clock output (cco): this outputs an external clock for use b y the application. table 2: peripheral clock gating bit assignments in clk_pckenr1/2 registers bit peripheral clock bit peripheral clock bit peripheral clock bit peripheral clock pcken17 tim1 pcken13 uart1 pcken27 reserved pcken23 adc pcken16 reserved pcken12 reserved pcken26 reserved pcken22 awu pcken15 tim2 pcken11 spi pcken25 reserved pcken21 reserved pcken14 tim4 pcken10 i 2 c pcken24 reserved pcken20 reserved
stm8s003k3 stm8s003f3 product overview docid018576 rev 4 15 / 95 4.6 power management for efficent power management, the application can be put in one of four different low - power modes. you can configure each mode to obtain the best compromise between lowest power consumption, fastest start - up time and available wakeup sources. x wait mode: in this mode, the cpu is stopped, but peripherals are kept running. the wakeup is performed by an internal or external interrupt or reset. x active halt mode with regulator on : in this mode, the cpu and peripheral clocks are stopped. an internal wakeup is generated at programmable intervals by the auto wake up unit (awu). the main voltage regulator is kept powered on, so current consumption is higher than in active halt mode wi th regulator off, but the wakeup time is faster. wakeup is triggered by the internal awu interrupt, external interrupt or reset. x active halt mode with regulator off: this mode is the same as active halt with regulator on, except that the main voltage regul ator is powered off, so the wake up time is slower. x halt mode: in this mode the microcontroller uses the least power. the cpu and peripheral clocks are stopped, the main voltage regulator is powered off. wakeup is triggered by external event or reset. 4.7 wat chdog timers the watchdog system is based on two independent timers providing maximum security to the applications. activation of the watchdog timers is controlled by option bytes or by software. once activated, the watchdogs cannot be disabled by the user program without performing a reset. window watchdog timer the window watchdog is used to detect the occurrence of a software fault, usually generated by external interfere nces or by unexpected logical conditions, which cause the application program to abandon its normal sequence. the window function can be used to trim the watchdog behavior to match the application perfectly. the application software must refresh the coun ter before time - out and during a limited time window. a reset is generated in two situations: 1. timeout: at 16 mhz cpu clock the time - out period can be adjusted between 75 s up to 64 ms. 2. refresh out of window: the downcounter is refreshed before its value is lower than the one stored in the window register. independent watchdog timer the independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or softw are failures. it is clocked by the 128 khz lsi internal rc clock source, and thus stays active even in case of a cpu clock failure the iwdg time base spans from 60 s to 1 s.
product overview stm8s003k3 stm8s003f3 16 / 95 docid018576 rev 4 4.8 auto wakeup counter x used for auto wakeup from active halt mode x clock source: internal 128 khz internal low frequency rc oscillator or external clock x lsi clock can be internally connected to tim1 input capture channel 1 for calibration 4.9 beeper the beeper function outputs a signal on the beep pin for sound generation. the signal is in the range of 1, 2 or 4 khz. the beeper output port is only available through the alternate function remap option bit afr7. 4.10 tim1 - 16 - bit advanced control timer this is a high - end timer designed for a wide range of control applications. with its complementary outputs, dead - time control and center - aligned pwm capability, the field of applications is extended to motor control, lighting and half - bridge driver x 16 - bit up, down and up/down autoreload counter with 16 - bit prescaler x four independent cap ture/compare channels (capcom) configurable as input capture, output compare, pwm generation (edge and center aligned mode) and single pulse mode output x synchronization module to control the timer with external signals x break input to force the timer outp uts into a defined state x three complementary outputs with adjustable dead time x encoder mode x interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break 4.11 tim2 - 16 - bit general purpose timer x 16 - bit autoreload (ar) up - counter x 15 - bit prescaler adjustable to fixed power of 2 ratios 132768
stm8s003k3 stm8s003f3 product overview docid018576 rev 4 17 / 95 4.12 tim4 - 8 - bit basic timer x 8 - bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128 x clock source: cpu clock x interrupt source: 1 x overflow/update table 3: tim timer features timer counter size (bits) prescaler counting mode capcom channels complem. outputs ext. trigger timer synchroniz ation/ chaining tim1 16 any integer from 1 to 65536 up/down 4 3 yes no tim2 16 any power of 2 from 1 to 32768 up 3 0 no tim4 8 any power of 2 from 1 to 128 up 0 0 no 4.13 analog - to - digital converter (adc1) the stm8s003xx products contain a 10 - bit successive approximation a/d converter (adc1) with up to 5 external multiplexed inputs channels and the following features: x input voltage range: 0 to v dd x input voltage range: 0 to v dda x conversion time: 14 clock cyc les x single and continuous and buffered continuous conversion modes x buffer size (n x 10 bits) where n = number of input channels x scan mode for single and continuous conversion of a sequence of channels x analog watchdog capability with programmable upper and lower thresholds x internal reference voltage on channel ain7 x analog watchdog interrupt x external trigger input x trigger from tim1 trgo x end of conversion (eoc) interrupt additional ain12 analog input is not selectable in adc scan mode or with analog watchdog. values converted from ain12 are stored only into the adc_drh/adc_drl registers. internal bandgap reference voltage channel ain7 is internally connected to the inte rnal bandgap reference voltage. the internal bandgap reference is constant and can be used, for example, to monitor v dd . it is independent of variations in v dd and ambient temperature t a . 4.14 communication interfaces the following communication interfaces are implemented: x uart1: full feature uart, synchronous mode, spi master mode, smartcard mode, irda mode, single wire mode, li n2.1 master capability x spi : full and half - duplex, 8 mbit/s
product overview stm8s003k3 stm8s003f3 18 / 95 docid018576 rev 4 x i2c: up to 400 kbit/s 4.14.1 uart1 main features x one mbit/s full duplex sci x spi emulation x high precision baud rate generator x smartcard emulation x irda sir encoder decoder x lin master mode x single wire half duplex mode asynchronous communication (uart mode) x full duplex communication - nrz standard format (mark/space) x programmable transmit and receive baud rates up to 1 mbit/s ( f cpu /16) and capable of following any standard baud rate regardless of the input frequency x separate enable bits for transmitter and receiver x two receiver wakeup modes: address bit (msb) idle line (interrupt) x transmission error detection with interrupt generation x parity control synchronous communication x full duplex synchronous transfers x spi master operation x 8 - bit data communication x maximum speed: 1 mbit/s at 16 mhz (f cpu /16) lin master mode x emission: generates 13 - bit synch break frame x reception: detects 11 - bit break frame 4.14.2 spi x maximum speed: 8 mbit/s (f master /2) both for master and slave x full duplex synchronous transfers x simplex synchronous transfers on two lines with a possible bidirectional data line x master or slave operation - selectable by hardware or software x crc calculation x 1 byte tx and rx buffer x slave/master selection input pin 4.14.3 i2c x i2c master features: clock generation start and stop generation x i2c slave features: programmable i2c address detection stop bit detection x generation and detection of 7 - bit/10 - bit addressing and general call x supports different communication speeds:
stm8s003k3 stm8s003f3 product overview docid018576 rev 4 19 / 95 standard speed (up to 100 khz) fast speed (up to 400 khz)
pinout and pin description stm8s003k3 stm8s003f3 20 / 95 docid018576 rev 4 5 pinout and pin description table 4: legend/abbreviations for pino ut tables type i= input, o = output, s = power supply level input cm = cmos output hs = high sink output speed o1 = slow (up to 2 mhz) o2 = fast (up to 10 mhz) o3 = fast/slow programmability with slow as default state after reset o4 = fast/slow programmability with fast as default state after reset port and control configuration input float = floating, wpu = weak pull - up output t = true open drain, od = open drain, pp = push pull reset state bold x (pin state after internal reset release). unless otherwise specified, the pin state is the same during the reset phase and after the internal reset release.
stm8s003k3 stm8s003f3 pinout and pin description docid018576 rev 4 21 / 95 5.1 stm8s003k3 lqfp32 pinout and pin description figure 3 : stm8s003k3 lqfp32 pinout 1. (hs) high sink capability. 2. (t) true open drain (p - buffer and protection diode to v dd not implemented). 3. [ ] alternate function remapping opt ion (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). table 5: lqfp32 pin description pin no. pin name ty pe input output main function (after reset) default alternate function alternate function after remap [option bit] floatin g wp u ext. interru pt high sink (1) spe ed od pp 1 nrst i/o x reset 2 pa1/ osci (2) i/o x x x o1 x x port a1 resonator/ crystal in 3 pa2/ oscout i/o x x x o1 x x port a2 resonator/ crystal out 4 v ss s digital ground i 2 c_scl/(t) pb4 tim1_etr/ain3/(hs) pb3 tim1_ch3n/ ain2/ (hs) pb2 tim1_ch2n/ ain1/(hs) pb1 tim1_ch1n/ain0/(hs) pb0 pb7 pb6 i 2 c_sda/ (t) pb5 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 1 1 12 13 14 15 16 1 2 3 4 5 6 7 8 vca p v dd [spi_nss] tim2_ch3/(hs) p a3 pf4 nrs t oscin/ p a1 oscout/ p a2 v ss pc3 (hs) /tim1_ch3 pc2 (hs) /tim1_ch2 pc1 (hs) /tim1_ch1/ ua r t1_ck pe5 (hs) /spi_nss pc7 (hs)/spi_miso pc6 (hs)/spi_mosi pc5 (hs)/spi_sck pc4 (hs) /tim1_ch4/clk_cco pd3 (hs)/tim2_ch2/adc_etr pd2 (hs) [tim2_ch3] pd1 (hs)/swim pd0 (hs)/ tim1_bkin [clk_cco] pd7 (hs)/tli [ tim1_ch4] pd6 (hs)/ua r t1_rx pd5 (hs)/ua r t1_tx pd4 (hs)/beep/tim2_ch1
pinout and pin description stm8s003k3 stm8s003f3 22 / 95 docid018576 rev 4 pin no. pin name ty pe input output main function (after reset) default alternate function alternate function after remap [option bit] floatin g wp u ext. interru pt high sink (1) spe ed od pp 5 vcap s 1.8 v regulator capacitor 6 v dd s digital power supply 7 pa3/ tim2_ch3 [spi_nss] i/o x x x hs o3 x x port a3 timer 2 channel 3 spi master/ slave select [afr1] 8 pf4 i/o x x o1 x x port f4 9 pb7 i/o x x x o1 x x port b7 10 pb6 i/o x x x o1 x x port b6 11 pb5/ i 2 c_sda i/o x x o1 t (3) port b5 i 2 c data 12 pb4/ i 2 c_scl i/o x x o1 t (3) port b4 i 2 c clock 13 pb3/ain3/ tim1_etr i/o x x x hs o3 x x port b3 analog input 3/ timer 1 external trigger 14 pb2/ain2/ tim1_ch3n i/o x x x hs o3 x x port b2 analog input 2/ timer 1 - inverted channel 3 15 pb1/ain1/ tim1_ch2n i/o x x x hs o3 x x port b1 analog input 1/ timer 1 - inverted channel 2 16 pb0/ain0/ tim1_ch1n i/o x x x hs o3 x x port b0 analog input 0/ timer 1 - inverted channel 1 17 pe5/ spi_nss i/o x x x hs o3 x x port e5 spi master/slave select 18 pc1/ tim1_ch1/ uart1_ck i/o x x x hs o3 x x port c1 timer 1 - channel 1 uart1 clock 19 pc2/ tim1_ch2 i/o x x x hs o3 x x port c2 timer 1 - channel 2 20 pc3/ tim1_ch3 i/o x x x hs o3 x x port c3 timer 1 - channel 3
stm8s003k3 stm8s003f3 pinout and pin description docid018576 rev 4 23 / 95 pin no. pin name ty pe input output main function (after reset) default alternate function alternate function after remap [option bit] floatin g wp u ext. interru pt high sink (1) spe ed od pp 21 pc4/ tim1_ch4/ clk_cco i/o x x x hs o3 x x port c4 timer 1 - channel 4 /configurable clock output 22 pc5/ spi_sck i/o x x x hs o3 x x port c5 spi clock 23 pc6/ pi_mosi i/o x x x hs o3 x x port c6 spi master out/slave in 24 pc7/ pi_miso i/o x x x hs o3 x x port c7 spi master in/ slave out 25 pd0/ tim1_bkin [clk_cco] i/o x x x hs o3 x x port d0 timer 1 - break input configurab le clock output [afr5] 26 pd1/ swim (4) i/o x x x hs o4 x x port d1 swim data interface 27 pd2 [tim2_ch3] i/o x x x hs o3 x x port d2 timer 2 - channel 3[afr1] 28 pd3/ tim2_ch2/ adc_etr i/o x x x hs o3 x x port d3 timer 2 - channel 2/adc external trigger 29 pd4/beep/ tim2_ch1 i/o x x x hs o3 x x port d4 timer 2 - channel 1/beep output 30 pd5/ uart1_tx i/o x x x hs o3 x x port d5 uart1 data transmit 31 pd6/ uart1_rx i/o x x x hs o3 x x port d6 uart1 data receive 32 pd7/ tli [tim1_ch4] i/o x x x hs o3 x x port d7 top level interrupt timer 1 - channel 4 [afr6] notes: (1) i/o pins used simultaneously for high current source/sink must be uniformly spaced around the package. in addition, the total driven current must respect the absolute maximum ratings (see section electrical characteristics?>. (2) when the mcu is in halt/a ctive - halt mode, pa1 is automatically configured in input weak pull - up and cannot be used for waking up the device. in this mode, the output state of pa1 is not driven. it is recommended to use pa1 only in input mode if halt/active - halt is used in the appl ication. (3) in the open - drain output column, "t" defines a true open - drain i/o (p - buffer, weak pull - up, and protection diode to v dd are not implemented). (4) the pd1 pin is in input pull - up during the reset phase and after internal reset release.
pinout and pin description stm8s003k3 stm8s003f3 24 / 95 docid018576 rev 4 5.2 stm8s003 f3 tssop20/ufqfpn20 pinout and pin description 5.2.1 stm8s003f3 tssop20 pinout and pin description figure 4 : stm8s003f3 tssop20 pinout 1. hs high sink capability. 2. (t) true open drain (p - buffer and protection diode to v dd not implemented). 3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 ua r t1_ck/tim2_ch1/beep/(hs) pd4 pd3 (hs)/ain4/tim2_ch2/adc_etr pd1(hs)/swim pb4 (t)/i2c_sc l [adc_etr] pc3 (hs)/tim1_ch3 [tli] [tim1_ch1n] pc4 (hs)/tim1_ch4/clk_cco/ain2/[tim1_ch2n] pc5 (hs)/spi_sck [tim2_ch1] 12 1 1 9 10 [spi_nss] tim2_ch3/(hs) p a3 pd2 (hs)/ain3/[tim2_ch3] pb5 (t)/i2c_sd a [tim1_bkin] ua r t1_tx/ain5/(hs) pd5 ua r t1_rx/ain6/(hs) pd6 pc6 (hs)/spi_mosi [tim1_ch1] pc7 (hs)/spi_miso [tim1_ch2] nrs t oscin/ p a1 oscout/ p a2 v ss vca p v dd
stm8s003k3 stm8s003f3 pinout and pin description docid018576 rev 4 25 / 95 5.2.2 stm8s003f3 ufqfpn20 pinout figure 5 : stm8s003f3 ufqfpn20 - pin pinout 1. hs high sink capability. 2. (t) true open drain (p - buffer and protection diode to v dd not implemented). 3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function).
pinout and pin descrip tion stm8s003k3 stm8s003f3 26 / 95 docid018576 rev 4 5.2.3 stm8s003f3 tssop20/ufqfpn20 pin description table 6: stm8s003f3 pin description pin no. pin name typ e input output main functi on (after reset) default alternate function alternate function after remap [option bit] tssop2 0 ufqfp n20 floati ng wp u ext. inte rr. high sink (1) spe ed od pp 1 18 pd4/ beep/ tim2_ ch1/ uart1 _ck i/o x x x hs o3 x x port d4 timer 2 - channel 1/beep output/ uart1 clock 2 19 pd5/ ain5/ uart1 _tx i/o x x x hs o3 x x port d5 analog input 5/ uart1 data transmit 3 20 pd6/ ain6/ uart1 _rx i/o x x x hs o3 x x port d6 analog input 6/ uart1 data receive 4 1 nrst i/o x reset 5 2 pa1/ oscin (2) i/o x x x o1 x x port a1 resonator/ crystal in 6 3 pa2/ oscout i/o x x x o1 x x port a2 resonator/ crystal out 7 4 v ss s digital ground 8 5 vcap s 1.8 v regulator capacitor 9 6 v dd s digital power supply 10 7 pa3/ tim2_ ch3 [spi_ nss] i/o x x x hs o3 x x port a3 timer 2 channel 3 spi master/ slave select [afr1] 11 8 pb5/ i 2 c_ sda [tim1_ bkin] i/o x x o1 t (3) port b5 i 2 c data timer 1 - break input [afr4] 12 9 pb4/ i 2 c_ scl i/o x x o1 t (3) port b4 i 2 c clock adc external trigger [afr4] 13 10 pc3/ tim1_ch3 [tli] [tim1_ ch1n] i/o x x x hs o3 x x port c3 timer 1 - channel 3 top level interrupt [afr3] timer 1 - inverted channel 1 [afr7]
stm8s003k3 stm8s003f3 pinout and pin description docid018576 rev 4 27 / 95 pin no. pin name typ e input output main functi on (after reset) default alternate function alternate function after remap [option bit] tssop2 0 ufqfp n20 floati ng wp u ext. inte rr. high sink (1) spe ed od pp 14 11 pc4/ clk_cco/ tim1_ ch4/ain2/[t im1_ ch2n] i/o x x x hs o3 x x port c4 configurabl e clock output/time r 1 - channel 4/analog input 2 timer 1 - inverted channel 2 [afr7] 15 12 pc5/ spi_sck [tim2_ ch1] i/o x x x hs o3 x x port c5 spi clock timer 2 - channel 1 [afr0] 16 13 pc6/ spi_mosi [tim1_ ch1] i/o x x x hs o3 x x port c6 spi master out/slave in timer 1 - channel 1 [afr0] 17 14 pc7/ spi_miso [tim1_ ch2] i/o x x x hs o3 x x port c7 spi master in/ slave out timer 1 - channel 2 [afr0] 18 15 pd1/ swim (4) i/o x x x hs o4 x x port d1 swim data interface 19 16 pd2/ain3/[ti m2_ ch3] i/o x x x hs o3 x x port d2 analog input 3 timer 2 - channel 3 [afr1] 20 17 pd3/ ain4/ tim2_ ch2/ adc_ etr i/o x x x hs o3 x x port d3 analog input 4/ timer 2 - channel 2/adc external trigger notes: (1) i/o pins used simultaneously for high current source/sink must be uniformly spaced around the package. in addition, the total driven current must respect the absolute maximum ratings. (2) when the mcu is in halt/active - halt mode, pa1 is automatically confi gured in input weak pull - up and cannot be used for waking up the device. in this mode, the output state of pa1 is not driven. it is recommended to use pa1 only in input mode if halt/active - halt is used in the application. (3) in the open - drain output column , "t" defines a true open - drain i/o (p - buffer, weak pull - up, and protection diode to v dd are not implemented). (4) the pd1 pin is in input pull - up during the reset phase and after internal reset release.
pinout and pin description stm8s003k3 stm8s003f3 28 / 95 docid018576 rev 4 5.3 alternate function remapping as shown in the rightmost column of the pin description table, some alternate functions can be remapped at different i/o ports by programming one of eight afr (alternate function rema p) option bits. when the remapping option is active, the default alternate function is no longer available. to use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. alternate function remapping does not effe ct gpio capabilities of the i/o ports (see the gpio section of the family reference manual, rm0016).
stm8s003k3 stm8s003f3 memory and register map docid018576 rev 4 29 / 95 6 memory and register map 6.1 memory map figure 6 : memory map
memory and regi ster map stm8s003k3 stm8s003f3 30 / 95 docid018576 rev 4 6.2 register map 6.2.1 i/o port hardware register map table 7: i/o port hardware register map address block register label register name reset status 0x00 5000 port a pa_odr port a data output latch register 0x00 0x00 5001 pa_idr port a input pin value register 0xxx (1) 0x00 5002 pa_ddr port a data direction register 0x00 0x00 5003 pa_cr1 port a control register 1 0x00 0x00 5004 pa_cr2 port a control register 2 0x00 0x00 5005 port b pb_odr port b data output latch register 0x00 0x00 5006 pb_idr port b input pin value register 0xxx (1) 0x00 5007 pb_ddr port b data direction register 0x00 0x00 5008 pb_cr1 port b control register 1 0x00 0x00 5009 pb_cr2 port b control register 2 0x00 0x00 500a port c pc_odr port c data output latch register 0x00 0x00 500b pb_idr port c input pin value register 0xxx (1) 0x00 500c pc_ddr port c data direction register 0x00 0x00 500d pc_cr1 port c control register 1 0x00 0x00 500e pc_cr2 port c control register 2 0x00 0x00 500f port d pd_odr port d data output latch register 0x00 0x00 5010 pd_idr port d input pin value register 0xxx (1) 0x00 5011 pd_ddr port d data direction register 0x00 0x00 5012 pd_cr1 port d control register 1 0x02 0x00 5013 pd_cr2 port d control register 2 0x00 0x00 5014 port e pe_odr port e data output latch register 0x00 0x00 5015 pe_idr port e input pin value register 0xxx (1) 0x00 5016 pe_ddr port e data direction register 0x00 0x00 5017 pe_cr1 port e control register 1 0x00 0x00 5018 port e pe_cr2 port e control register 2 0x00 0x00 5019 port f pf_odr port f data output latch register 0x00 0x00 501a pf_idr port f input pin value register 0xxx (1) 0x00 501b pf_ddr port f data direction register 0x00 0x00 501c pf_cr1 port f control register 1 0x00 0x00 501d pf_cr2 port f control register 2 0x00 notes: (1) depends on the external circuitry.
stm8s003k3 stm8s003f3 memory and register map docid018576 rev 4 31 / 95 6.2.2 general hardware register map table 8: general hardware register map address block register label register name reset status 0x00 501e to 0x005059 reserved area (60 bytes) 0x00 505a flash flash_cr1 flash control register 1 0x00 0x00 505b flash_cr2 flash control register 2 0x00 0x00 505c flash_ncr2 flash complementary control register 2 0xff 0x00 505d flash _fpr flash protection register 0x00 0x00 505e flash _nfpr flash complementary protection register 0xff 0x00 505f flash _iapsr flash in - application programming status register 0x00 0x00 5060 to 0x005061 reserved area (2 bytes) 0x00 5062 flash flash _pukr flash program memory unprotection register 0x00 0x00 5063 reserved area (1 byte) 0x00 5064 flash flash_dukr data eeprom unprotection register 0x00 0x00 5065 to 0x00 509f reserved area (59 bytes) 0x00 50a0 itc exti_cr1 external interrupt control register 1 0x00 0x00 50a1 exti_cr2 external interrupt control register 2 0x00 0x00 50a2 to 0x0050b2 reserved area (17 bytes) 0x00 50b3 rst rst_sr reset status register 0xxx (1) 0x00 50b4 to 0x0050bf reserved area (12 bytes) 0x00 50c0 clk clk_ickr internal clock control register 0x01 0x00 50c1 clk_eckr external clock control register 0x00 0x00 50c2 reserved area (1 byte) 0x00 50c3 clk clk_cmsr clock master status register 0xe1 0x00 50c4 clk_swr clock master switch register 0xe1 0x00 50c5 clk_swcr clock switch control register 0xxx 0x00 50c6 clk_ckdivr clock divider register 0x18 0x00 50c7 clk_pckenr1 peripheral clock gating register 1 0xff
memory and register map stm8s003k3 stm8s003f3 32 / 95 docid018576 rev 4 address block register label register name reset status 0x00 50c8 clk_cssr clock security system register 0x00 0x00 50c9 clk_ccor configurable clock control register 0x00 0x00 50ca clk_pckenr2 peripheral clock gating register 2 0xff 0x00 50cc clk_hsitrimr hsi clock calibration trimming register 0x00 0x00 50cd clk_swimccr swim clock control register 0bxx xx xxx0 0x00 50ce to 0x00 50d0 reserved area (3 bytes) 0x00 50d1 wwdg wwdg_cr wwdg control register 0x7f 0x00 50d2 wwdg_wr wwdr window register 0x7f 0x00 50d3 to 00 50df reserved area (13 bytes) 0x00 50e0 iwdg iwdg_kr iwdg key register 0xxx (2) 0x00 50e1 iwdg_pr iwdg prescaler register 0x00 0x00 50e2 iwdg_rlr iwdg reload register 0xff 0x00 50e3 to 0x00 50ef reserved area (13 bytes) 0x00 50f0 awu awu_csr1 awu control/status register 1 0x00 0x00 50f1 awu_apr awu asynchronous prescaler buffer register 0x3f 0x00 50f2 awu_tbr awu timebase selection register 0x00 0x00 50f3 beep beep_csr beep control/status register 0x1f 0x00 50f4 to 0x0050ff reserved area (12 bytes) 0x00 5200 spi spi_cr1 spi control register 1 0x00 0x00 5201 spi_cr2 spi control register 2 0x00 0x00 5202 spi_icr spi interrupt control register 0x00 0x00 5203 spi_sr spi status register 0x02 0x00 5204 spi_dr spi data register 0x00 0x00 5205 spi_crcpr spi crc polynomial register 0x07 0x00 5206 spi_rxcrcr spi rx crc register 0xff 0x00 5207 spi_txcrcr spi tx crc register 0xff
stm8s003k3 stm8s003f3 memory and register map docid018576 rev 4 33 / 95 address block register label register name reset status 0x00 5208 to 0x00 520f reserved area (8 bytes) 0x00 5210 i 2 c i2c_cr1 i 2 c control register 1 0x00 0x00 5211 i2c_cr2 i 2 c control register 2 0x00 0x00 5212 i2c_freqr i 2 c frequency register 0x00 0x00 5213 i2c_oarl i 2 c own address register low 0x00 0x00 5214 i2c_oarh i 2 c own address register high 0x00 0x00 5215 reserved 0x00 5216 i2c_dr i 2 c data register 0x00 0x00 5217 i2c_sr1 i 2 c status register 1 0x00 0x00 5218 i2c_sr2 i 2 c status register 2 0x00 0x00 5219 i2c_sr3 i 2 c status register 3 0x0x 0x00 521a i2c_itr i 2 c interrupt control register 0x00 0x00 521b i2c_ccrl i 2 c clock control register low 0x00 0x00 521c i2c_ccrh i 2 c clock control register high 0x00 0x00 521d i2c_triser i 2 c trise register 0x02 0x00 521e i2c_pecr i 2 c packet error checking register 0x00 0x00 521f to 0x00 522f reserved area (17 bytes) 0x00 5230 uart1 uart1_sr uart1 status register 0xc0 0x00 5231 uart1_dr uart1 data register 0xxx 0x00 5232 uart1_brr1 uart1 baud rate register 1 0x00 0x00 5233 uart1_brr2 uart1 baud rate register 2 0x00 0x00 5234 uart1_cr1 uart1 control register 1 0x00 0x00 5235 uart1_cr2 uart1 control register 2 0x00 0x00 5236 uart1_cr3 uart1 control register 3 0x00 0x00 5237 uart1_cr4 uart1 control register 4 0x00 0x00 5238 uart1_cr5 uart1 control register 5 0x00 0x00 5239 uart1_gtr uart1 guard time register 0x00 0x00 523a uart1_pscr uart1 prescaler register 0x00 0x00 523b to 0x00 523f reserved area (21 bytes) 0x00 5250 tim1 tim1_cr1 tim1 control register 1 0x00 0x00 5251 tim1_cr2 tim1 control register 2 0x00
memory and register map stm8s003k3 stm8s003f3 34 / 95 docid018576 rev 4 address block register label register name reset status 0x00 5252 tim1_smcr tim1 slave mode control register 0x00 0x00 5253 tim1_etr tim1 external trigger register 0x00 0x00 5254 tim1_ier tim1 interrupt enable register 0x00 0x00 5255 tim1_sr1 tim1 status register 1 0x00 0x00 5256 tim1_sr2 tim1 status register 2 0x00 0x00 5257 tim1_egr tim1 event generation register 0x00 0x00 5258 tim1_ccmr1 tim1 capture/compare mode register 1 0x00 0x00 5259 tim1_ccmr2 tim1 capture/compare mode register 2 0x00 0x00 525a tim1_ccmr3 tim1 capture/compare mode register 3 0x00 0x00 525b tim1_ccmr4 tim1 capture/compare mode register 4 0x00 0x00 525c tim1_ccer1 tim1 capture/compare enable register 1 0x00 0x00 525d tim1_ccer2 tim1 capture/compare enable register 2 0x00 0x00 525e tim1_cntrh tim1 counter high 0x00 0x00 525f tim1_cntrl tim1 counter low 0x00 0x00 5260 tim1_pscrh tim1 prescaler register high 0x00 0x00 5261 tim1_pscrl tim1 prescaler register low 0x00 0x00 5262 tim1_arrh tim1 auto - reload register high 0xff 0x00 5263 tim1_arrl tim1 auto - reload register low 0xff 0x00 5264 tim1_rcr tim1 repetition counter register 0x00 0x00 5265 tim1_ccr1h tim1 capture/compare register 1 high 0x00 0x00 5266 tim1_ccr1l tim1 capture/compare register 1 low 0x00 0x00 5267 tim1_ccr2h tim1 capture/compare register 2 high 0x00 0x00 5268 tim1_ccr2l tim1 capture/compare register 2 low 0x00 0x00 5269 tim1_ccr3h tim1 capture/compare register 3 high 0x00 0x00 526a tim1_ccr3l tim1 capture/compare register 3 low 0x00
stm8s003k3 stm8s003f3 memory and register map docid018576 rev 4 35 / 95 address block register label register name reset status 0x00 526b tim1_ccr4h tim1 capture/compare register 4 high 0x00 0x00 526c tim1_ccr4l tim1 capture/compare register 4 low 0x00 0x00 526d tim1_bkr tim1 break register 0x00 0x00 526e tim1_dtr tim1 dead - time register 0x00 0x00 526f tim1_oisr tim1 output idle state register 0x00 0x00 5270 to 0x00 52ff reserved area (147 bytes) 0x00 5300 tim2 tim2_cr1 tim2 control register 1 0x00 0x00 5301 reserved 0x00 5302 reserved 0x00 5303 tim2_ier tim2 interrupt enable register 0x00 0x00 5304 tim2_sr1 tim2 status register 1 0x00 0x00 5305 tim2_sr2 tim2 status register 2 0x00 0x00 5306 tim2_egr tim2 event generation register 0x00 0x00 5307 tim2_ccmr1 tim2 capture/compare mode register 1 0x00 0x00 5308 tim2_ccmr2 tim2 capture/compare mode register 2 0x00 0x00 5309 tim2_ccmr3 tim2 capture/compare mode register 3 0x00 0x00 530a tim2_ccer1 tim2 capture/compare enable register 1 0x00 0x00 530b tim2_ccer2 tim2 capture/compare enable register 2 0x00 0x00 530c tim2_cntrh tim2 counter high 0x00 0x00 530d tim2_cntrl tim2 counter low 0x00 0x00 530e tim2_pscr tim2 prescaler register 0x00 0x00 530f tim2_arrh tim2 auto - reload register high 0xff 0x00 5310 tim2_arrl tim2 auto - reload register low 0xff 0x00 5311 tim2_ccr1h tim2 capture/compare register 1 high 0x00 0x00 5312 tim2_ccr1l tim2 capture/compare register 1 low 0x00 0x00 5313 tim2_ccr2h tim2 capture/compare reg. 2 high 0x00
memory and register map stm8s003k3 stm8s003f3 36 / 95 docid018576 rev 4 address block register label register name reset status 0x00 5314 tim2_ccr2l tim2 capture/compare register 2 low 0x00 0x00 5315 tim2_ccr3h tim2 capture/compare register 3 high 0x00 0x00 5316 tim2_ccr3l tim2 capture/compare register 3 low 0x00 0x00 5317 to 0x00 533f reserved area (43 bytes) 0x00 5340 tim4 tim4_cr1 tim4 control register 1 0x00 0x00 5341 reserved 0x00 5342 reserved 0x00 5343 tim4_ier tim4 interrupt enable register 0x00 0x00 5344 tim4_sr tim4 status register 0x00 0x00 5345 tim4_egr tim4 event generation register 0x00 0x00 5346 tim4_cntr tim4 counter 0x00 0x00 5347 tim4_pscr tim4 prescaler register 0x00 0x00 5348 tim4_arr tim4 auto - reload register 0xff 0x00 5349 to 0x00 53df reserved area (153 bytes) 0x00 53e0 to 0x00 53f3 adc1 adc _dbxr adc data buffer registers 0x00 0x00 53f4 to 0x00 53ff reserved area (12 bytes) 0x00 5400 adc1 adc _csr adc control/status register 0x00 0x00 5401 adc_cr1 adc configuration register 1 0x00 0x00 5402 adc_cr2 adc configuration register 2 0x00 0x00 5403 adc_cr3 adc configuration register 3 0x00 0x00 5404 adc_drh adc data register high 0xxx 0x00 5405 adc_drl adc data register low 0xxx 0x00 5406 adc_tdrh adc schmitt trigger disable register high 0x00 0x00 5407 adc_tdrl adc schmitt trigger disable register low 0x00 0x00 5408 adc_htrh adc high threshold register high 0x03 0x00 5409 adc_htrl adc high threshold register low 0xff 0x00 540a adc_ltrh adc low threshold register high 0x00
stm8s003k3 stm8s003f3 memory and register map docid018576 rev 4 37 / 95 address block register label register name reset status 0x00 540b adc_ltrl adc low threshold register low 0x00 0x00 540c adc_awsrh adc analog watchdog status register high 0x00 0x00 540d adc_awsrl adc analog watchdog status register low 0x00 0x00 540e adc _awcrh adc analog watchdog control register high 0x00 0x00 540f adc_awcrl adc analog watchdog control register low 0x00 0x00 5410 to 0x00 57ff reserved area (1008 bytes) notes: (1) depends on the previous reset source. (2) write only register. 6.2.3 cpu/swim/debug module/interrupt controller registers table 9: cpu/swim/debug module/interrupt controller registers address block register label register name reset status 0x00 7f00 cpu (1) a accumulator 0x00 0x00 7f01 pce program counter extended 0x00 0x00 7f02 pch program counter high 0x00 0x00 7f03 pcl program counter low 0x00 0x00 7f04 xh x index register high 0x00 0x00 7f05 xl x index register low 0x00 0x00 7f06 yh y index register high 0x00 0x00 7f07 yl y index register low 0x00 0x00 7f08 sph stack pointer high 0x03 0x00 7f09 spl stack pointer low 0xff 0x00 7f0a ccr condition code register 0x28 0x00 7f0b to 0x00 7f5f reserved area (85 bytes) 0x00 7f60 cpu cfg_gcr global configuration register 0x00 0x00 7f70 itc itc_spr1 interrupt software priority register 1 0xff 0x00 7f71 itc_spr2 interrupt software priority register 2 0xff 0x00 7f72 itc_spr3 interrupt software priority register 3 0xff
memory and register map stm8s003k3 stm8s003f3 38 / 95 docid018576 rev 4 address block register label register name reset status 0x00 7f73 itc_spr4 interrupt software priority register 4 0xff 0x00 7f74 itc_spr5 interrupt software priority register 5 0xff 0x00 7f75 itc_spr6 interrupt software priority register 6 0xff 0x00 7f76 itc_spr7 interrupt software priority register 7 0xff 0x00 7f77 itc_spr8 interrupt software priority register 8 0xff 0x00 7f78 to 0x00 7f79 reserved area (2 bytes) 0x00 7f80 swim swim_csr swim control status register 0x00 0x00 7f81 to 0x00 7f8f reserved area (15 bytes) 0x00 7f90 dm dm_bk1re dm breakpoint 1 register extended byte 0xff 0x00 7f91 dm_bk1rh dm breakpoint 1 register high byte 0xff 0x00 7f92 dm_bk1rl dm breakpoint 1 register low byte 0xff 0x00 7f93 dm_bk2re dm breakpoint 2 register extended byte 0xff 0x00 7f94 dm_bk2rh dm breakpoint 2 register high byte 0xff 0x00 7f95 dm_bk2rl dm breakpoint 2 register low byte 0xff 0x00 7f96 dm_cr1 dm debug module control register 1 0x00 0x00 7f97 dm_cr2 dm debug module control register 2 0x00 0x00 7f98 dm_csr1 dm debug module control/status register 1 0x10 0x00 7f99 dm_csr2 dm debug module control/status register 2 0x00 0x00 7f9a dm_enfctr dm enable function register 0xff 0x00 7f9b to 0x00 7f9f reserved area (5 bytes) notes: (1) accessible by debug module only
stm8s003k3 stm8s003f3 interrupt vector mapping docid018576 rev 4 39 / 95 7 interrupt vector mapping table 10: interrupt mapping irq no. source block description wakeup from halt mode wakeup from active - halt mode vector address reset reset yes yes 0x00 8000 trap software interrupt - - 0x00 8004 0 tli external top level interrupt - - 0x00 8008 1 awu auto wake up from halt - yes 0x00 800c 2 clk clock controller - - 0x00 8010 3 exti0 port a external interrupts yes (1) yes (1) 0x00 8014 4 exti1 port b external interrupts yes yes 0x00 8018 5 exti2 port c external interrupts yes yes 0x00 801c 6 exti3 port d external interrupts yes yes 0x00 8020 7 exti4 port e external interrupts yes yes 0x00 8024 8 reserved - - 0x00 8028 9 reserved - - 0x00 802c 10 spi end of transfer yes yes 0x00 8030 11 tim1 tim1 update/ overflow/ underflow/ trigger/ break - - 0x00 8034 12 tim1 tim1 capture/ compare - - 0x00 8038 13 tim2 tim2 update/ overflow - - 0x00 803c 14 tim2 tim2 capture/ compare - - 0x00 8040 15 reserved - - 0x00 8044 16 reserved - - 0x00 8048 17 uart1 tx complete - - 0x00 804c 18 uart1 receive register data full - - 0x00 8050 19 i 2 c i 2 c interrupt yes yes 0x00 8054 20 reserved - - 0x00 8058 21 reserved - - 0x00 805c 22 adc1 adc1 end of conversion/ analog watchdog interrupt - - 0x00 8060 23 tim4 tim4 update/ overflow - - 0x00 8064 24 flash eop/wr_pg_dis - - 0x00 8068 reserved 0x00 806c to 0x00 807c notes: (1) except pa1.
option bytes stm8s003k3 stm8s003f3 40 / 95 docid018576 rev 4 8 option bytes option bytes contain configurations for device hardware features as well as the memory protection of the device. they are stored in a dedicated block of the memory. except for the rop (read - out protection) byte, each option byte has to be stored twice, in a regular form (optx) and a complemented one (noptx) for redundancy. option bytes can be modified in icp mode (via swim) by accessing the eeprom address shown in the table below. option bytes can also be modified on the fly by the application in iap mo
stm8s003k3 stm8s003f3 option bytes docid018576 rev 4 41 / 95 table 12: option byte description option byte no. description opt0 rop[7:0] memory readout protection (rop) 0xaa: enable readout protection (write access via swim protocol) note: refer to the family reference manual (rm0016) section on flash/eeprom memory readout protection for deta ils. opt1 ubc[7:0] user boot code area 0x00: no ubc, no write - protection 0x01: page 0 defined as ubc, memory write - protected 0x02: pages 0 to 1 defined as ubc, memory write - protected. page 0 and 1 contain the interrupt vectors. ... 0x7f: pages 0 to 126 defined as ubc, memory write - protected other values: pages 0 to 127 defined as ubc, memory write - protected note: refer to the family reference manual (rm0016) section on flash write protection for more details. opt2 afr[7:0] refer to following section for alternate function remapping decriptions of bits [7:2] and [1:0] respectively. opt3 hsitrim :high speed internal clock trimming register size 0: 3 - bit trimming supported in clk_hsitrimr register 1: 4 - bit trimming support ed in clk_hsitrimr register lsi_en :low speed internal clock enable 0: lsi clock is not available as cpu clock source 1: lsi clock is available as cpu clock source iwdg_hw : independent watchdog 0: iwdg independent watchdog activated by software 1: iwdg independent watchdog activated by hardware wwdg_hw : window watchdog activation 0: wwdg window watchdog activated by software 1: wwdg window watchdog activated by hardware wwdg_halt : window watchdog reset on halt 0: no reset generated on ha lt if wwdg active 1: reset generated on halt if wwdg active
option bytes stm8s003k3 stm8s003f3 42 / 95 docid018576 rev 4 option byte no. description opt4 extclk : external clock selection 0: external crystal connected to oscin/oscout 1: external clock signal on oscin ckawusel :auto wake - up unit/clock 0: lsi clock source selected for awu 1: hse clock with prescaler selected as clock source for for awu prsc[1:0] awu clock prescaler 0x: 16 mhz to 128 khz prescaler 10: 8 mhz to 128 khz prescaler 11: 4 mhz to 128 khz prescaler opt5 hsecnt[7:0] :hse crystal oscillator stabilization time 0x00: 2048 hse cycles 0xb4: 128 hse cycles 0xd2: 8 hse cycles 0xe1: 0.5 hse cycles
stm8s003k3 stm8s003f3 option bytes docid018576 rev 4 43 / 95 8.1 alternate function remapping bits table 13: stm8s003k3 alternate function remapping bits for 32 - pin devices option byte no. description (1) opt2 afr7 alternate function remapping option 7 reserved. afr6 alternate function remapping option 6 0: afr6 remapping option inactive: default alternate function (2) 1: port d7 alternate function = tim1_ch4. afr5 alternate function remapping option 5 0: afr5 remapping option inactive: default alternate function (2) 1: port d0 alternate function = clk_cco. afr[4:2] alternate function remapping options 4:2 reserved. afr1 alternate function remapping option 1 0: afr1 remapping option inactive: default alternate functions (2) 1: port a3 alternate function = spi_nss; port d2 alternate function = tim2_ch3. afr0 alternate function remapping option 0 reserved. notes: (1) do not use more than one remapping option in the same port. it is forbidden to enable bo th afr1 and afr0. (2) refer to pinout description.
option bytes stm8s003k3 stm8s003f3 44 / 95 docid018576 rev 4 table 14: stm8s003f3 alternate function remapping bits for 20 - pin devices option byte no. description opt2 afr7 alternate function remapping option 7 0: afr7 remapping option inactive: default alternate functions. (1) 1: port c3 alternate function = tim1_ch1n; port c4 alternate function = tim1_ch2n. afr6 alternate function remapping option 6 reserved. afr5 alternate function remapping option 5 reserved. afr4 alternate function remapping option 4 0: afr4 remapping option inactive: default alternate functions. (2) 1: port b4 alternate function = adc_etr; port b5 alternate function = tim1_bkin. afr3 alternate function remapping option 3 0: afr3 remapping option inactive: default alternate function. (1) 1: port c3 alternate function = tli. afr2 alternate function remapping option 2 reserved afr1 alternate function remapping option 1 (2) 0: afr1 remapping option inactive: default alternate functions. 1: port a3 alternate function = spi_nss; port d2 alternate function = tim2_ch3. afr0 alternate function remapping option 0 (2) 0: afr0 remapping option inactive: default alternate functions. 1: port c5 alternate function = tim2_ch1; port c6 alternate function = tim1_ch1; port c7 alternate function = tim1_ch2. notes: (1) refer to pinout description. (2) do not use more than one remapping option in t he same port. it is forbidden to enable both afr1 and afr0.
stm8s003k3 stm8s003f3 electrical characteristics docid018576 rev 4 45 / 95 9 electrical characteristics 9.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 9.1.1 minimum and maximum values unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at t a = 25 c and t a = t amax (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). or equal to the value indicated (mean 2 ). 5 0 p f stm 8 p i n stm 8 p i n v in
electrical characteristics stm8s003k3 stm8s003f3 46 / 95 docid018576 rev 4 9.2 absolute maximum ratings stresses above those listed as absolute maximum ratings may cause permanent damage
stm8s003k3 stm8s003f3 electrical characteristics docid018576 rev 4 47 / 95 table 16: current characteristics symbol ratings max (1) unit i vdd total current into v dd power lines (source). (2) 100 ma i vss total current out of v ss ground lines (sink) (2) 80 i io output current sunk by any i/o and control pin 20 output current source by any i/os and control pin - 20 i inj(pin) (3) (4) injected current on nrst pin 4 injected current on oscin pin 4 injected current on any other pin (5) 4 i and i when several inputs are submitted to a current injection, the maximum i on characterization with i
electrical characteristics stm8s003k3 stm8s003f3 48 / 95 docid018576 rev 4 9.3 operating conditions table 18: general operating conditions symbol parameter conditions min max unit f cpu internal cpu clock frequency 0 16 mhz v dd standard operating voltage 2.95 5.5 v vcap (1) c ext : capacitance of external capacitor 470 3300 nf esr of external capacitor at 1 mhz (2) - 0.3 )/ given in the previous table and the value for
stm8s003k3 stm8s003f3 electrical characteristics docid018576 rev 4 49 / 95 table 19: operating conditions at power - up/power - down symbol parameter conditions min typ max unit t vdd v dd rise time rate 2 s/v c rlea k es r e s l
electrical characteristics stm8s003k3 stm8s003f3 50 / 95 docid018576 rev 4 9.3.2.1 total current consumption in run mode the mcu is placed under the following conditions: x all i/o pins in input mode with a static value at v dd or v ss (no load) x all peripherals are disabled (clock stopped by peripheral clock gating registers) except if exp licitly mentioned. subject to general operating conditions for v dd and t a . table 20: total current consumption with code execution in run mode at vdd= 5 v symbol parameter conditions typ max (1) unit i dd(run) supply current in run mode, code executed from ram f cpu = f master = 16 mhz hse crystal osc. (16 mhz) 2.3 - ma hse user ext. clock (16 mhz) 2 2.35 hsi rc osc. (16 mhz) 1.7 2 f cpu = f master /128 = 125 khz hse user ext. clock (16 mhz) 0.86 - hsi rc osc. (16 mhz) 0.7 0.87 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) 0.46 0.58 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.41 0.55 supply current in run mode, code executed from flash f cpu = f master = 16 mhz hse crystal osc. (16 mhz) 4.5 - hse user ext. clock (16 mhz) 4.3 4.75 hsi rc osc. (16 mhz) 3.7 4.5 i dd(run) supply current in run mode, code executed from flash f cpu = f master = 2 mhz hsi rc osc. (16 mhz/8) (2) 0.84 1.05 ma f cpu = f master /128 = 125 khz hsi rc osc. (16 mhz) 0.72 0.9 f cpu = f master /128 = 15.625khz hsi rc osc. (16 mhz/8) 0.46 0.58 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.42 0.57 notes:
stm8s003k3 stm8s003f3 electrical characteristics docid018576 rev 4 51 / 95 (1) data based on characterization results, not tested in production. (2) default clock configuration measured with all peripherals off. table 21: total current consumption with code execution in run mode at vdd= 3.3 v symbol parameter conditions typ max (1) unit i dd(run) supply current i n run mode, code executed from ram f cpu = f master = 16 mhz hse crystal osc. (16 mhz) 1.8 ma hse user ext. clock (16 mhz) 2 2.3 hsi rc osc. (16 mhz) 1.5 2 f cpu = f master /128 = 125 khz hse user ext. clock (16 mhz) 0.81 hsi rc osc. (16 mhz) 0.7 0.87 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) 0.46 0.58 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.41 0.55 supply current in run mode, code executed from flash f cpu = f master = 16 mhz hse crystal osc. (16 mhz) 4 hse user ext. clock (16 mhz) 3.9 4.7 hsi rc osc. (16 mhz) 3.7 4.5 f cpu = f master = 2 mhz hsi rc osc. (16 mhz/8) (2) 0.84 1.05 f cpu = f master /128 = 125 khz hsi rc osc. (16 mhz) 0.72 0.9 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) 0.46 0.58 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.42 0.57 notes: (1) data based on characterization results, not tested in production. (2) default clock configuration measured with all peripherals off.
electrical characteristics stm8s003k3 stm8s003f3 52 / 95 docid018576 rev 4 9.3.2.2 total current consumption in wait mode table 22: total current consumption in wait mode at vdd= 5 v symbol parameter conditions typ max (1) unit i dd(wfi) supply current in wait mode f cpu = f master = 16 mhz hse crystal osc. (16 mhz) 1.6 - ma hse user ext. clock (16 mhz) 1.1 1.3 hsi rc osc. (16 mhz) 0.89 1.1 f cpu = f master /128 = 125 khz hsi rc osc. (16 mhz) 0.7 0.88 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) (2) 0.45 0.57 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.4 0.54 notes: (1) data based on characterization results, not tested in production. (2) default clock configuration measured with all peripherals off. table 23: total current consumption in wait mode at vdd= 3.3 v symbol parameter conditions typ max (1) unit i dd(wfi) supply current in wait mode f cpu = f master = 16 mhz hse crystal osc. (16 mhz) 1.1 - ma hse user ext. clock (16 mhz) 1.1 1.3 hsi rc osc. (16 mhz) 0.89 1.1 f cpu = f master /128 = 125 khz hsi rc osc. (16 mhz) 0.7 0.88 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) (2) 0.45 0.57 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.4 0.54 notes: (1) data based on characterization results, not tested in production. (2) default clock configuration measured with all peripherals off.
stm8s003k3 stm8s003f3 electrical characteristics docid018576 rev 4 53 / 95 9.3.2.3 total current consumption in active halt mode table 24: total current consumption in active halt mode at vdd= 5 v symbol parameter conditions typ max at 85 c (1) unit main voltage regulator (mvr) (2) flash mode (3) clock source i dd(ah) supply current in active halt mode on operating mode hse crystal osc. (16 mhz) 1030 - a a a
electrical characteristics stm8s003k3 stm8s003f3 54 / 95 docid018576 rev 4 symbol parameter conditions typ max at 85 c (1) unit main voltage regulator (mvr) (2) flash mode (3) clock source i dd(ah) power - down mode (128 khz) 10 18 notes: (1) data based on characterization results, not tested in production. (2) configured by the regah bit in the clk_ickr register. (3) configured by the ahalt bit in the flash_cr1 register. 9.3.2.4 total current consumption in halt mode table 26: total current consumption in halt mode at vdd= 5 v symbol parameter conditions typ max at 85c (1) unit i dd(h) supply current in halt mode flash in operating mode, hsi clock after wakeup 63 75 a a
stm8s003k3 stm8s003f3 electrical characteristics docid018576 rev 4 55 / 95 symbol parameter conditions typ max (1) unit t wu(wfi) wakeup time from wait mode to run mode (2) 0 to 16 mhz - see note (3) s s s s s s s s
electrical characteristics stm8s003k3 stm8s003f3 56 / 95 docid018576 rev 4 9.3.2.6 total current consumption and timing in forced reset state table 29: total current consumption and timing in forced reset state symbol parameter conditions typ max (1) unit i dd(r) supply current in reset state (2) v dd = 5 v 400 - a s a
stm8s003k3 stm8s003f3 electrical characteristics docid018576 rev 4 57 / 95 9.3.2.8 current consumption curves the following figures show typical current consumption measured with code executing in ram. figure 11 : typ idd(run) vs. vdd hse user external clock, fcpu = 16 mhz figure 12 : typ idd(run) vs. fcpu hse user external clock, vdd = 5 v
electrical characteristics stm8s003k3 stm8s003f3 58 / 95 docid018576 rev 4 figure 1 3 : typ idd(run) vs. vdd hsi rc osc, fcpu = 16 mhz figure 14 : typ idd(wfi) vs. vdd hse user external clock, fcpu = 16 mhz figure 15 : typ idd(wfi) vs. fcpu hse user external clock, vdd = 5 v
stm8s003k3 stm8s003f3 electrical characteristics docid018576 rev 4 59 / 95 figure 16 : typ idd(wfi) vs. vdd hsi rc osc, fcpu = 16 mhz 9.3.3 external clock sources and timing characteristics hse user external clock subject to general operating conditions for v dd and t a . table 31: hse user external clock characteristics symbol parameter conditions min max unit f hse_ext user external clock source frequency - 0 16 mhz v hseh (1) oscin input pin high level voltage 0.7 x v dd v dd + 0.3 v v v hsel (1) oscin input pin low level voltage v ss 0.3 x v dd i leak_hse oscin input leakage current v ss < v in < v dd - 1 +1 a
electrical characteristics stm8s003k3 stm8s003f3 60 / 95 docid018576 rev 4 hse crystal/ceramic resonator oscillator the hse clock can be supplied with a 1 to 16 mhz crystal/ceramic resonator oscillator. all the information given in this paragraph is based on characterization r esults with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start - up stabilization time. refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...). table 32: hse oscillator characteristics symbol parameter conditions min typ max unit f hse external high speed oscillator frequency 1 - 16 mhz r f feedback resistor - - 220 - k?
stm8s003k3 stm8s003f3 electrical characteristics docid018576 rev 4 61 / 95 g mcrit = (2 f 40 c t 85 c s a
electrical characteristics stm8s003k3 stm8s003f3 62 / 95 docid018576 rev 4 figure 19 : typical hsi frequency variation vs vdd@ 4 temperatures low speed internal rc oscillator (lsi) subject to general operating conditions for v dd and t a . table 34: lsi oscillator characteristics symbol parameter typ max unit f lsi frequency 128 - khz t su(lsi) lsi oscillator wake - up time - 7 s a
stm8s003k3 stm8s003f3 electrical cha racteristics docid018576 rev 4 63 / 95 9.3.5 memory characteristics ram and hardware registers table 35: ram and hardware registers symbol parameter conditions min unit v rm data retention mode (1) ha lt mode (or reset) v it - max (2) v notes: (1) minimum supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware registers (only in halt mode). guaranteed by design, not tested in production. (2) refer to the operating conditions section for the value of v it - max flash program memory and data eeprom table 36: flash program memory and data eeprom symbol parameter conditions min (1) typ max unit v dd operating voltage (all modes, execution/write/erase) f cpu 16 mhz
electrical characteristics stm8s003k3 stm8s003f3 64 / 95 docid018576 rev 4 (1) data based on characterization results, not tested in production. (2) the physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte.> 9.3.6 i/o port pin characteristics general characteristics subject to general operating conditions for v dd and t a unless otherwise specified. all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull - up or pull - down resistor. table 37: i/o static characteristics symbol parameter conditions min typ ma x unit v il input low level voltage v dd = 5 v - 0.3v - 0.3 x v dd v v ih input high level voltage 0.7 x v dd - v dd + 0.3 v hys hysteresis (1) - 700 - mv r pu pull - up resistor v dd = 5 v, v in = v ss 30 55 80 k v v a v v a
stm8s003k3 stm8s003f3 electrical characteristics docid018576 rev 4 65 / 95 figure 21 : typical viland vihvs vdd@ 4 temperatures figure 22 : typical pull - up resistance vs vdd@ 4 temperatures figure 23 : typical pull - up current vs vdd@ 4 temperatures
electrical characteristics stm8s003k3 stm8s003f3 66 / 95 docid018576 rev 4 table 38: output driving current (standard ports) symbol parameter conditions min max unit v ol output low level with 8 pins sunk i io = 10 ma, v dd = 5 v - 2.0 v output low level with 4 pins sunk i io = 4 ma, v dd = 3.3 v - 1.0 (1) v oh output high level with 8 pins sourced i io = 10 ma, v dd = 5 v 2.8 - output high level with 4 pins sourced i io = 4 ma, v dd = 3.3 v 2.1 (1) - notes: (1) data based on characterisation results, not tested in production.> table 39: output driving current (true open drain ports) symbol parameter conditions max unit v ol output low level with 2 pins sunk i io = 10 ma, v dd = 5 v 1 .0 v v ol output low level with 2 pins sunk i io = 10 ma, v dd = 3.3 v 1.5 (1) v ol output low level with 2 pins sunk i io = 20 ma, v dd = 5 v 2.0 (1) notes: (1) data based on characterisation results, not tested in production.> table 40: output driving current (high sink ports) symbol parameter conditions min max unit v ol output low level with 8 pins sunk i io = 10 ma, v dd = 5 v - 0.8 v v ol output low level with 4 pins sunk i io = 10 ma, v dd = 3.3 v - 1.0 (1) v output low level with 4 pins sunk i io = 20 ma, v dd = 5 v - 1.5 (1) v oh output high level with 8 pins sourced i io = 10 ma, v dd = 5 v 4.0 - output high level with 4 pins sourced i io = 10 ma, v dd = 3.3 v 2.1 (1) -
stm8s003k3 stm8s003f3 electrical characteristics docid018576 rev 4 67 / 95 symbol parameter conditions min max unit output high level with 4 pins sourced i io = 20 ma, v dd = 5 v 3.3 (1) - notes: (1) data based on characterisation results, not tested in production.> figure 24 : typ. vol@ vdd= 5 v (standard ports) figure 25 : typ. vol@ vdd= 3.3 v (standard ports)
electrical characteristics stm8s003k3 stm8s003f3 68 / 95 docid018576 rev 4 figure 26 : typ. vol@ vdd= 5 v (true open drain ports) figure 27 : typ. vol@ vdd= 3.3 v (true open drain ports)
stm8s003k3 stm8s003f3 electrical characteristics docid018576 rev 4 69 / 95 figure 28 : typ. vol@ vdd= 5 v (high sink ports) figure 29 : typ. vol@ vdd= 3.3 v (high sink ports)
electrical characteristics stm8s003k3 stm8s003f3 70 / 95 docid018576 rev 4 figure 30 : typ. vdd - voh@ vdd= 5 v (standard ports) figure 31 : typ. vdd - voh@ vdd= 3.3 v (standard ports)
stm8s003k3 stm8s003f3 electrical characteristics docid018576 rev 4 71 / 95 figure 32 : typ. vdd - voh@ vdd= 5 v (high sink ports) figure 33 : typ. vdd - voh@ vdd= 3.3 v (high sink ports)
electrical characteristics stm8s003k3 stm8s003f3 72 / 95 docid018576 rev 4 9.3.7 reset pin characteristics subject to general operating conditions for v dd and t a unless otherwise specified. table 41: nrst pin characteristics symbol parameter conditions min typ max unit v i l(nrst) nrst input low level voltage (1) - - 0.3 v - 0.3 x v dd v v ih(nrst) nrst input high level voltage (1) i ol =2 ma 0.7 x v dd - v dd + 0.3 v ol(nrst) nrst output low level voltage (1) - - - 0.5 r pu(nrst) nrst pull - up resistor (2) - 30 55 80 k s
stm8s003k3 stm8s003f3 electrical characteristics docid018576 rev 4 73 / 95 figure 35 : typical nrst pull - up resistance v s vdd@ 4 temperatures figure 36 : typical nrst pull - up current vs vdd@ 4 temperatures the reset network shown in the following figure protects the device against parasitic resets. the user must ensure that the level on the nrst p in can go below v il(nrst) max., otherwise the reset is not taken into account internally. for power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. if nrst signal is used to reset external circuitry, attention must be taken to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. minimum recommended capacity is 10 nf.
electrical characteristics stm8s003k3 stm8s003f3 74 / 95 docid018576 rev 4 figure 37 : recommended reset pin prot ection 9.3.8 spi serial peripheral interface unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, f master frequency and v dd supply voltage conditions. t master = 1/f master . refer to i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso). table 42: spi characteristics symbol parameter conditions (1) min max unit f sck 1/ t c(sck) spi clock frequency master mode 0 8 mhz f sck 1/ t c(sck) f sck 1/ t c(sck) spi clock frequency 0 7 (2) mhz t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 30 pf - 25 ns t su(nss) (3) nss setup time slave mode 4 x t master - t h(nss) (3) nss hold time slave mode 70 - t w(sckh) (3) t w(sckl) (3) sck high and low time master mode t sck / 2 - 15 t sck / 2 +15 t su(mi) (3) t su(si) (3) data input setup time master mode 5 - slave mode 5 - t h(mi) (3) t h(si) (3) data input hold time master mode 7 - slave mode 10 - t a(so) (3) (4) data output access time slave mode - 3 x t master t dis(so) (3) (5 ) data output disable time slave mode 25 - t v(so) (3) data output valid time slave mode (after enable edge) - 65 (2) external reset circuit (optional) 0.1 f nrst vdd rpu filter internal reset stm8
stm8s003k3 stm8s003f3 electrical characteristics docid018576 rev 4 75 / 95 symbol parameter conditions (1) min max unit t v(mo) (3) data output valid time master mode (after enable edge) - 30 t h(so) (3) data output hold time slave mode (after enable edge) 27 (2) - t h(mo) (3) data output hold time master mode (after enable edge) 11 (2) - notes: (1) parameters are given by selecting 10 mhz i/o output frequency. (2) data characterization in progress. (3) values based on design simulation and/or characterization results, and not tested in production.> (4) min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. (5) min time is for the minimum time to invalidate the output and the max time to put the data in hi - z. figure 38 : spi timing diagram - slave mode and cpha = 0 figure 39 : spi timing diagram - slave mode and cpha = 1 1. measurement points are made at cmos levels: 0.3 vdd and 0.7 vdd.
electrical characteristics stm8s003k3 stm8s003f3 76 / 95 docid018576 rev 4 figure 40 : spi timing diagram - mas ter mode(1) 1. measurement points are made at cmos levels: 0.3 vdd and 0.7 vdd.
stm8s003k3 stm8s003f3 electrical characteristics docid018576 rev 4 77 / 95 9.3.9 i2c interface characteristics table 43: i2c characteristics symbol parameter standard mode i 2 c fast mode i 2 c (1) unit min (2) max (2) min (2) max (2) t w(scll) scl clock low time 4.7 - 1.3 - s s s
electrical charact eristics stm8s003k3 stm8s003f3 78 / 95 docid018576 rev 4 figure 41 : typical application with i2c bus and timing diagram 1. measurement points are made at cmos levels: 0.3 x vdd and 0.7 x vdd. 9.3.10 10 - bit adc characteristics subject to general operating conditions for v dd , f master , and t a unless otherwise specified. table 44: adc characteristics symbol parameter conditions min typ max u nit f adc adc clock frequency v dd =2.95 to 5.5 v 1 - 4 mhz v dd =4.5 to 5.5 v 1 - 6 v ain conversion voltage range (1) - v ss - v dd v c adc internal sample and hold capacitor - - 3 - pf t s (1) minimum sampling time f adc = 4 mhz - 0.75 - s s s s
stm8s003k3 stm8s003f3 electrical characteristics docid018576 rev 4 79 / 95 table 45: adc accuracy with rain< 10 k , vdd= 5 v and i table 46: adc accuracy with rain< 10 k rain, vdd= 3.3 v
electrical characteristics stm8s003k3 stm8s003f3 80 / 95 docid018576 rev 4 notes: (1) data based on characterization results, not tested in production. (2) adc accuracy vs. negative injection current: injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being per formed on another analog input. it is recommended to add a schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. any positive injection current within the limits specified for i inj(pin) and i
stm8s003k3 stm8s003f3 electrical characteristics docid018576 rev 4 81 / 95 figure 43 : typical application with adc 9.3.11 emc characteristics susceptibility tests are performed on a sample basis during product characterization. 9.3.11.1 functional ems (electromagnetic susceptibility) while executing a simple application (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic events until a failure occurs (indic ated by the leds). x fesd: functional electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 61000 - 4 - 2 standard. x ftb: a burst of fast transient voltage (po sitive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test conforms with the iec 61000 - 4 - 4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709 (emc design guide for stmicrocontrollers). 9.3.11.2 designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. prequalification trials most of the common fai lures (unexpected reset and program counter corruption) can be recovered by applying a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specificatio n values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring. see application note an1015 (software techniques for improving microcontroller emc performance). table 47: ems data symbol parameter conditions level/ class stm8 10-bit a/d conversion r ain c ain v ain ainx v dd v t 0.6 v v t 0.6 v i l 1 a c adc
el ectrical characteristics stm8s003k3 stm8s003f3 82 / 95 docid018576 rev 4 symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, t a = 25 c, f master = 16 mhz (hsi clock), conforming to iec 61000 - 4 - 2 2/b (1) v eftb fast transient vo ltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, t a = 25 c ,f master = 16 mhz (hsi clock),conforming to iec 61000 - 4 - 4 4/a (1) notes: (1) data obtained with hsi clock configuration, after applying hw recommendations described in an2860 (emc guidelines for stm8s microcontrollers). 9.3.11.3 electromagnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emission. this emission test is in line with the norm sae iec 61967 - 2 which specifies the board and t he loading of each pin. table 48: emi data symbol parameter conditions unit general conditions monitored frequency band max f hse /f cpu (1) 16 mhz/ 8 mhz 16 mhz/ 16 mhz s emi peak level v dd = 5 v, t a = 25 c, lqfp32 package. conforming to sae iec 61967 - 2 0.1mhz to 30mhz 5 5 dbv
stm8s003k3 stm8s003f3 electrical characteristics docid018576 rev 4 83 / 95 9.3.11.5 electrostatic discharge (esd) electrostati c discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). one model can be simulated: human body model. this test conforms to the jesd22 - a114a/a115a standard. for more details, refer to the application note an1181. table 49: esd absolute maximum ratings symbol ratings conditions class maximum value (1) unit v esd(hbm) electrostatic discharge voltage (human body model) t a = 25c, conforming to jesd22 - a114 a 4000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = 25c, conforming to sd22 - c101 lqfp32 package iv 1000 notes: (1) data based on characterization results, not tested in production. 9.3.11.6 static latch - up two complementary static tests are required on 10 part s to assess the latch - up performance: x a supply overvoltage (applied to each power supply pin) x a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch - up standard. for more details, refer to the application note an1181. table 50: electrical sensitivities symbol parameter conditions class (1) lu static latch - up clas s t a = 25 c a t a = 85 c a notes: (1) class description: a class is an stmicroelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jedec criteria (international standard).
package information stm8s003k3 stm8s003f3 84 / 95 docid018576 rev 4 10 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack ? is an st trademark. 10.1 32 - pin lqfp package mechanical data figure 44 : 32 - pin low profile quad flat package (7 mm x 7 mm) d d1 d3 e3 e1 e 1 8 9 16 17 24 25 32 a1 l1 l k a1 a2 a c b g a uge plane 0.25 mm se a ting plane c pin 1 identific a tion ccc c 5v_me_v2 e
stm8s003k3 stm8s003f3 package information docid018576 rev 4 85 / 95 table 51: 32 - pin low profile quad flat package mechanical data dim. mm inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 0.200 0.0035 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 5.600 0.2205 e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 5.600 0.2205 e 0.800 0.0315 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 0.0 3.5 7.0 0.0 3.5 7.0 ccc 0.100 0.0039 notes: (1) values in inches are converted from mm and rounded to 4 decimal digits
package information stm8s003k3 stm8s003f3 86 / 95 docid018576 rev 4 10.2 20 - pin tssop package mechanical data figure 45 : 20 - pin, 4.40 mm body, 0.65 mm pitch table 52: 20 - pin, 4.40 mm body, 0.65 mm pitch mechanical data dim. mm inches (1) min typ max min typ max a - - 1.200 - - 0.0472 a1 0.050 - 0.150 0.0020 - 0.0059 a2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 - 0.300 0.0075 - 0.0118 c 0.090 - 0.200 0.0035 - 0.0079 d (2) 6.400 6.500 6.600 0.2520 0.2559 0.2598 e 6.200 6.400 6.600 0.2441 0.2520 0.2598 e1 (3) 4.300 4.400 4.500 0.1693 0.1732 0.1772 e - 0.650 - - 0.0256 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 0.0 - 8.0 0.0 - 8.0 aaa - - 0.100 - - 0.0039 notes: (1) values in inches are converted from mm and rounded to 4 decimal digits (2) dimension "d" does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs
stm8s003k3 stm8s003f3 package information docid018576 rev 4 87 / 95 shall not exceed 0.15mm per side. (3) dimension "e1" does not include interlead flash or protru sions. interlead flash or protrusions shall not exceed 0.25mm per side. 10.3 20 - lead ufqfpn package mechanical data figure 46 : 20 - lead, ultra thin, fine pitch quad flat no - lead package outline (3 x 3) 1. drawing is not to scale. a0a5_me_v3 15 16 20 1 5 d e b e e a1 a ddd l2 10 l1 a3 l5 l4 d e top view side view bottom view pin 1 l3
package information stm8s003k3 stm8s003f3 88 / 95 docid018576 rev 4 table 53: 20 - lead, ultra thin, fine pitch quad flat no - lead package (3 x 3) package mechanical data dim. mm inches a min typ max min typ max d - 3.000 - - 0.1181 - e - 3.000 - - 0.1181 - a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 0.000 0.020 0.050 0.0000 0.0008 0.0020 a3 - 0.152 - - 0.0060 - e - 0.500 - - 0.0197 - l1 0.500 0.550 0.600 0.0197 0.0217 0.0236 l2 0.300 0.350 0.400 0.0118 0.0138 0.0157 l3 - 0.375 - - 0.0148 - l4 - 0.200 - - 0.0079 - l5 - 0.150 - - 0.0059 - b 0.180 0.250 0.300 0.0071 0.0098 0.0118 ddd - 0.050 - - 0.0020 - a values in inches are converted from mm and rounded to 4 decimal digits.
stm8s003k3 stm8s003f3 thermal characteristics docid018576 rev 4 89 / 95 11 thermal characteristics the maximum chip junction temperature (t jmax ) must never exceed the values given in section 7.5: "clock controller" . the maximum chip - junction temperature, t jmax , in degrees celsius, may be calculated using the following equation: t jmax = t amax + (p dmax x = (v ) + ((v
thermal characteristics stm8s003k3 stm8s003f3 90 / 95 docid018576 rev 4 x p dmax = 400 mw + 64 mw thus: p dmax = 464 mw t jmax for lqfp32 can be calculated as follows, using the thermal resistance
stm8s003k3 stm8s003f3 ordering information docid018576 rev 4 91 / 95 12 ordering information figure 47 : stm8s003x value line ordering information scheme 1. tssop and ufqfpn package. 2. lqfp package. for a list of available options (e.g. package, packing) and orderable part numbers or for further information on any aspect of this device, please go to ww w.st.com or contact the st sales office nearest to you. pin count k = 32 pins f = 20 pins example: sub-family type 00x = v alue line 003 sub-family family type s = standard t emperature range 6 = -40 c to 85 c program memory size 3 = 8 kbytes packing no character = t ray or tube tr = t ape and reel package pitch blank = 0.5 or 0.65 mm( 1) c = 0.8 mm (2) stm8 s 003 k 3 t 6 tr product class stm8 microcontroller package type 1 p = tsso p t = lqf p u = ufqfpn
stm8 development tools stm8s003k3 stm8s003f3 92 / 95 docid018576 rev 4 13 stm8 development tools development tools for the stm8 microcontrollers include the full - featured stice emulati on system supported by a complete software tool package including c compiler, assembler and integrated development environment with high - level language debugger. in addition, the stm8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low - cost in - circuit debugger/programmer. 13.1 emulation and in - circuit debugging tools the stice emulation system offers a complete r ange of emulation and in - circuit debugging features on a platform that is designed for versatility and cost - effectiveness. in addition, stm8 application development is supported by a low - cost in - circuit debugger/programmer. the stice is the fourth generat ion of full featured emulators from stmicroelectronics. it offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. in addi tion, stice offers in - circuit debugging and programming of stm8 microcontrollers via the stm8 single wire interface module (swim), which allows non - intrusive debugging of an application while it runs on the target microcontroller. for improved cost effect iveness, stice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future st microcontrollers. stice key features x occurrence and time profiling and code coverage (new features) x advanced breakpoints with up to 4 levels of conditions x data breakpoints x program and data trace recording up to 128 kb records x read/write on the fly of memory during emulation x in - circuit debugging/programming via swim protocol x 8 - bit probe analyzer x 1 input and 2 output triggers x power supply follower managing application voltages between 1.62 to 5.5 v x modularity that allows you to specify the components you need to meet your d evelopment requirements and adapt to future requirements x supported by free software tools that include integrated development environment (ide), programming software interface and assembler for stm8. 13.2 software tools stm8 development tools are supported by a complete, free software package from stmicroelectronics that includes st visual develop (stvd) ide and the st visual programmer (stvp) software interface. stvd provides sea mless integration of the cosmic and raisonance c compilers for stm8, which are available in a free version that outputs up to 16 kbytes of code. 13.2.1 stm8 toolset stm8 toolset with stvd integrated development environment and stvp programming software is available for free download at www.st.com/mcu. this package includes:
stm8s003k3 stm8s003f3 stm8 development tools docid018576 rev 4 93 / 95 st visual develop C st visual programmer (stvp) C write and verify of your stm8 microcontrollers flash program memory, data eeprom and cosmic c compiler for stm8 C raisonance c compiler for stm8 C stm8 assembler linker C
revision history stm8s003k3 stm8s003f3 94 / 95 docid018576 rev 4 14 revision history table 55: document revision history date revision changes 12 - jul - 2011 1 initial revision. 09 - jan - 2012 2 added n rw and t ret for data eeprom in table 36: "flash program memory and data eeprom" . updated r pu in table 41: "nrst pin characteristics" and table 37: "i/o static characteristics" . updated notes related to v cap in table 18: "general operating conditions" . 12 - jun - 2012 3 updated temperature condition for factory calibrated acc hsi in tab le 33: "hsi oscillator characteristics" . changed sck input to sck output in figure 40: "spi timing diagram - master mode(1)" modified figure 46: "20 - lead, ultra thin, fine pitch quad flat n o - lead package outline (3 x 3)" to add package top view. 18 - dec - 2014 4 updated the package information for the 20 - pin tssop and the 20 - pin ufqfpn.
stm8s003k3 stm8s003f3 docid018576 rev 4 95 / 95 important notice C stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or design of purchasers products. C

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